Input delay
Let us suppose that FPGA_1 needs to communicate with outside world as shown in figure.
In the figure, the routing delays and logic cloud makes DATA_IN signal to consume 4 ns to arrive at input port of FPGA_1. This arrival time of 4 ns is called input delay. So, input delay can be defined as the time consumed outside of FPGA_1 before the DATA_IN signal arrives at input port.
Significance of input delay
Let us say, clock period = 10ns.
In the absence of any IO constraint, FPGA_1 is completely oblivious to the non-zero arrival time of DATA_IN signal and assumes that whole 10 ns is available for input-port to reg_2 path. This is fine till FPGA_1 is the whole design and does not need to communicate to the outside world. In real world scenarios, communication with outside world is inevitable and so input port should be constrained accordingly.
When input delay (= 4 ns) is defined, the combo path from input port of FPGA_1 to reg_2 (first internal flop) will be constrained to 6 ns (clock period – input delay).
Please note that input delay constraint can also be put on IO port.
Output delay
Output delay can be defined as the time consumed outside of FPGA_1 in order to properly clock the driven device.
Consider the following figure.
Clock period = 10 ns; Output delay = 4 ns
=> 4 ns is the time required to clock reg_4 and the combo path from the clock pin of reg_3 flop of the current design to output port should be constrained to 6 ns (clock period – output delay).
Please note that output delay constraint can also be put on IO port.
