There are 3 important parameters associated with a flip flop or register. These are
a) Setup time
b) Hold time
Active clock can be either rising edge (i.e. 0 à 1 transition for positive edge triggered flip flop) or falling edge (i.e. 1 à 0 transition for negative edge triggered flip flop).
Propagation delay (tcq) is the clock-to-output delay i.e. data input (D) is available at output (Q) after a tcq delay.
The following waveform diagram depicts the definition of setup time, hold time and propagation delay. It is shown that data input is held constant for “tsu + thold “and flip flop takes tcq time to produce output data.
Now consider the simple system of two flip flops and the combo path between these as shown in following figure. The switching events are triggered with reference to positive edge of clock CLK i.e. the rising edge of clock denotes the beginning and completion of clock cycle.
Under the ideal scenario, Tclk1 = Tclk2 = T.
Clock period T should be long enough for the data to propagate through the flip flop and combo logic and to be setup at the destination flip flop before the next active edge. In essence, T must accommodate the
a) tcq(max), maximum clock-to-output delay.
b) tcomb(max), worst case combo path between the two flip flops.
c) tsu, setup time of flip flop.
i.e. T ≥ tcq(max) + tcomb(max) + tsu - eq 1
There is one more constraint imposed by hold time, thold, of flip flop. This constraint ensures that the data input is held constant after the active clock edge.
tcq(min) + tcomb(min) ≥ thold - eq2
Please note that hold time does not play any role in deciding clock period/frequency.
In the real world, neither Tclk1 ≠ Tclk2 nor clocks are perfectly periodic.
Let us first add clock skew to the above system.
Impact of clock skew on timing equations
It’s possible that clock does not reach the two flip flops simultaneously, probably due to mismatch in the clock path or differences in the clock load. This spatial variation in arrival time of clock is called clock skew. Clock skew can be positive or negative depending on routing direction of clock.
The following timing diagram shows that there is positive skew of tskew i.e. clock reaches reg_1 first and tclk2 lags tclk1 by tskew time.
Please note that clock skew only results in phase shift and not in clock period variation. Also the phase shift (i.e. skew) remains constant from cycle to cycle.
Data input D sampled by reg_1 on edge_1 propagates through combo logic and then sampled by reg_2 on edge_4. Since the clock skew is positive, “T + tskew” time is available for the data to propagate through reg_1 to reg_2
ð T + tskew ≥ tcq(max) + tcomb(max) + tsu - eq 3
If the propagation delay from reg_1 to reg_2 is very small, data shall reach reg_2 before edge_2 which in turn may result in race between clock and data. So the hold time constraint now is defined as
tcq(min) + tcomb(min) ≥ thold + tskew - eq 4
The same equations holds true for negative skew, just the value of tskew will be negative.
Now let us introduce clock jitter also.
Impact of clock jitter
Clock jitter is uncertainty or temporal variation in the clock period. Jitter can reduce or expand clock period on cycle to cycle basis.
Under worst case scenario, jitter can reduce clock period to “T - 2 tjitter” as shown in following fig.
ð T + tskew – 2 tjitter ≥ tcq(max) + tcomb(max) + tsu - eq 5 (modification of eq 3)
For the hold time constraint assume that jitter advances rising edge of CLK1 and delays that of CLK2 as shown in following fig.
Now to avoid race between clock and data, minimum propagation delay should define hold constraint as
tcq(min) + tcomb(min) – 2 tjitter ≥ thold + tskew - eq 6
