Timing considerations for flip flop (Setup and Hold time)

There are 3 important parameters associated with a flip flop or register. These are

a)     Setup time

b)    Hold time

c)     Propagation delay

Full case and Parallel case

We assume that you understand case (casez, casex) statement as well as if-else statement. So, the focus is on full_case and parallel_case directives.

The synthesis directives are added as a comment immediately after the case expression and before any of the case items as shown below.

case (case_expression) // synopsys full_case parallel_case

case_item1       : statement1;

case_item2       : statement2;

default          : statement3;

endcase

Typical ASIC Design Flow

What is Register Retiming?

Retiming is an optimizing algorithm for improving the circuit performance. It moves registers across combo-logic without affecting the functionality of design at primary input/output ports. Registers shall be added and to or removed from the design while performing retiming. However, additional registers do not add clock latency to the design’s performance.

IO constraints (Input delay, Output delay)

Input delay

Let us suppose that FPGA_1 needs to communicate with outside world as shown in figure.